Is for loop synthesizable in Verilog?

Related questions

1. What is synthesizable and non synthesizable?
2. What is the difference between SystemVerilog packed and unpacked array?
3. What is the difference between initial and final block of Systemverilog?
4. Why is default clocking block required?
5. Can we use for loop in Verilog?
6. Is generate statement synthesizable?
7. Is for loop synthesizable in VHDL?
8. Is always block synthesizable?
9. What does synthesizable mean in VHDL?
10. What is HDL in VHDL?

Tags

1. #construct
2. #verilog
3. #however
4. #statement
5. #synthesised
6. #combinational
7. #loops
8. #statements
9. #expanded
10. #inside
11. #constructed
12. #blocks
13. #synthesizable
14. #always
15. #synthesizing
16. #while
17. #should