Can we use for loop in Verilog?

Related questions

1. What is synthesizable and non synthesizable?
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6. What are synthesizable and non synthesizable constructs?
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Tags

1. #within
2. #begin
3. #while
4. #statements
5. #combine
6. #procedural
7. #using
8. #repeated
9. #execution
10. #repeat
11. #instruction
12. #block
13. #control
14. #verilog
15. #forever
16. #looping
17. #electrosofts
18. #should