What are synthesizable and non synthesizable constructs?

Related questions

1. What is always and forever?
2. What does synthesizable mean?
3. What does synthesizable mean in VHDL?
4. What is the difference between initial and always in Verilog?
5. What are signals in VHDL?
6. Is for forever grammatically correct?
7. What is the difference between SystemVerilog packed and unpacked array?
8. Can we use assign statement in always block?
9. Why is initial block not synthesizable?
10. Why is default clocking block required?

Tags

1. #converted
2. #testbenches
3. #simulation
4. #statements
5. #design
6. #gates
7. #piece
8. #easier
9. #synthesis
10. #verilog
11. #logic
12. #involves
13. #synthesizeable
14. #synthesizable
15. #system
16. #constructs