What is the difference between initial and always in Verilog?

Related questions

1. What does synthesizable mean?
2. What is synthesizable RTL?
3. What is synthesizable and non synthesizable?
4. Is generate statement synthesizable?
5. Is always block synthesizable?
6. Can we use assign statement in always block?
7. What's the difference between forever and always?
8. Is initial block in Verilog synthesizable?
9. What does synthesizable mean in VHDL?
10. What is always and forever?

Tags

1. #execute
2. #forever
3. #statements
4. #advance
5. #process
6. #whereas
7. #execution
8. #occasionally
9. #blocked
10. #between
11. #advances
12. #contain
13. #block
14. #allow
15. #always
16. #initial
17. #repeatedly
18. #processes
19. #difference
20. #timing