What's the difference between forever and always?

Related questions

1. What is the difference between initial and final block of Systemverilog?
2. Why always is used in Verilog?
3. What is initial begin in Verilog?
4. What is difference between Verilog and VHDL?
5. What is HDL in VHDL?
6. Is for loop synthesizable in VHDL?
7. Can we use for loop in Verilog?
8. What does always * mean in Verilog?
9. What does synthesizable mean?
10. What is the Do While function?

Tags

1. #relevant
2. #forever
3. #there
4. #differ
5. #answers
6. #syntactically
7. #means
8. #continuously
9. #other
10. #amount
11. #future
12. #difference
13. #contexts
14. #always
15. #usually
16. #infinite
17. #times
18. #whereas