Is generate statement synthesizable?

Related questions

1. Why is default clocking block required?
2. What is forever in Verilog?
3. Why always is used in Verilog?
4. What does synthesizable mean?
5. What does synthesizable mean in VHDL?
6. What are signals in VHDL?
7. What is the difference between initial and final block of Systemverilog?
8. Is for loop synthesizable in VHDL?
9. What is synthesizable and non synthesizable?
10. Can we use for loop in Verilog?

Tags

1. #possible
2. #inside
3. #verilog
4. #generate
5. #block
6. #synthesizer
7. #basically
8. #unrolling
9. #synthesizeable
10. #generator
11. #directive
12. #statement
13. #assign