Can subprograms be overloaded?

Related questions

1. What is FPGA hardware?
2. What is Modelling in VHDL?
3. What is subprogram in VHDL?
4. What is instantiation in VHDL?
5. What is data flow Modelling in VHDL?
6. What is Xilinx iMPACT?
7. What is identifier in VHDL?
8. What is package declaration in VHDL?
9. What is generic map in VHDL?
10. What do you mean by function and variables write about VHDL variables?

Tags

1. #types
2. #every
3. #operator
4. #return
5. #unique
6. #order
7. #meanings
8. #different
9. #others
10. #parameters
11. #function
12. #procedure
13. #number
14. #overloaded
15. #protocol
16. #multiple
17. #incarnation
18. #subprograms